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- Article name
- SIMULATION OF FIELD PROGRAMMABLE GATE ARRAYS ON VERILOG HDL
- Authors
- Kurganskiy S. I., , skurg@mail.ru, Voronezh State University, Joint Stock Company «Engineering and design centre "Electronics"», Voronezh, Russia
Tsirlov M. A., , macwork@mail.ru, Voronezh State University, Joint Stock Company «Engineering and design centre "Electronics"», Voronezh, Russia
Matyushin D. V., , dvladimir@tut.by, Joint Stock Company «Engineering and design centre Electronics», Voronezh, Russia
- Keywords
- simulation / FPGA / Verilog HDL / BSIM3v3
- Year
- 2010 Issue 4 Pages 48 - 51
- Code EDN
- Code DOI
- Abstract
- This paper is dedicated to one of the most perspective semiconductor devices - field programmable gate arrays (FPGA) and their verification. Wode popularity of FPGA devices is based on its flexible logic, provided by architecture redundancy. Architecture complexity leads to the rise of device price, and as a result project verification becomes more significant. In this paper the stages of digital device model development are demonstrated. Possibility to take into account physical processes in the model, observed in semiconductor devices, is shown.
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